1. Field of the Invention
The present invention relates generally to a semiconductor memory, more particularly, to a semiconductor memory equipped with a row address decoder having a reduced signal propagation delay time.
2. Description of the Related Art
In a semiconductor memory, a row address is decoded by a decoder circuit to activate a single word line in a memory cell array.
FIG. 13 shows a decoder circuit for decoding a 2-bit row address with four 2-input NAND gates.
In this circuit scheme, 2.sup.N N-input NAND gates are required in a case of an N-bit row address . The N-input NAND gates having 2.sup.N outputs are disposed beside a memory cell array in order to decrease a total length of all interconnecting lines. However, when a value N is larger, the size of N-input NAND gate circuit increases, therefore the row pitch of memory cell is so larger that the memory density of the memory cell decreases.
Hence, a row address decoder circuit has been made to have a two stage configuration divided into a pre-decoder on the row address input side and a main decoder on the memory cell array side.
FIG. 14 shows a prior art 4-bit row address decoder circuit.
The pre-decoder 10 consists of a 2-bit decoder 11 for lower 2 bits A1 and A0 and a 2-bit decoder 12 for higher 2 bits A3 and A2. One of 4 outputs from the 2-bit decoder 11 and one of 4 outputs from the 2-bit decoder 12 are combined and all the combinations are provided to individual 2-input NAND gates in a main decoder 20.
The number of row address bits increases with increase in a storage capacity of a semiconductor memory, leading to a larger length of interconnecting lines between the pre-decoder 10 and the main decoder 20. Generally speaking, when a row address increases by one bit, the average length of interconnection lines between a pre-decoder and a main decoder increases to be twofold. When the length of interconnection line becomes twofold, each of a resistance value and a capacitance value thereof becomes twofold, causing a CR delay to be fourfold, with the result that rising and falling edge of a signal become gentle. Hence, an access time in a semiconductor memory increases to hinder a high-speed operation thereof.
FIG. 15 is a layout sketch of circuit blocks in a prior art semiconductor chip.
An address control circuit 30 includes an address buffer circuit, an address buffer register, and the pre-decoder, for receiving an address and providing a predecoded signal. The main decoder 20 provides a row select signal onto a word line of memory cell arrays MC1 to MC4.
Contents of memory cells connected to an activated word line in the memory cell arrays MC1 to MC4 are provided to a data I/O control circuit 33 or 34 through bit lines. Each of the data I/O control circuits 33 and 34 includes sense amplifiers amplifying signals on bit lines, and column switches selecting an amplified signal according to a column address.
In order to achieve a fast operation with reducing a propagation delay time, in the prior art, such a configuration as FIG. 16 was adopted. In FIG. 16, the address control circuit 30 of FIG. 15 is divided into address control circuits 30A and 30B, and an address control circuit 30A and a main decoder 20A are provided for the memory cell arrays MC1 and MC2, an address control circuit 30B and a main decoder 20B are provided for the memory cell arrays MC3 and MC4, and data I/O control circuits 33A, 34A, 33B and 34B are provided for the memory cell arrays MC1, MC2, MC3 and MC4, respectively.
However, there is an increase in the chip area of the semiconductor memory, resulting in higher cost compared with the configuration of FIG. 15.
This problem is solved by adopting a configuration shown in FIG. 17 in which the address control circuit 30 is disposed in a central portion, the data I/O control circuit 33 is disposed between the memory cell arrays MC1 and MC3, and the data I/O control circuit 34 is disposed between the memory cell arrays MC2 and MC4.
However, when the memory cell arrays MC1 to MC4 each become longer in a bit line direction in order to increase a storage capacity, the same problem as that of FIG. 15 arises. Moreover, when the data I/O control circuits are distributed as shown in FIG. 16 in order to solve the same problem as that of FIG. 15, the same problem as that of FIG. 16 then arises.